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december 2002 copyright ? alliance semiconductor. all rights reserved. ? AS7C33256NTD16A as7c33256ntd18a 12/2/02 , v.1.7 alliance semiconductor p. 1 of 10

tm features ? organization: 262,144 words 16 or 18 bits ntd ?1 architecture for ef ficient bus operation fast clock speeds to 166 mhz in lvttl/lvcmos fast clock to data access: 3.5/4.0/5.0 ns fast oe access time: 3.5/4.0/5.0 ns fully synchronous operation flow-through or pipelined mode asynchronous output enable control 1 ntd is a trademark of alliance semiconductor corporation. economical 100-pin tqfp package byte write enables clock enable for operation hold multiple chip enable s for easy expansion 3.3v core power supply 2.5v or 3.3v i/o operation with separate v ddq 30 mw typical standby power self-timed write cycles interleaved or linear burst modes snooze mode for standby operation write buffer address d q clk register output register dq [a:b] 16/18 16/18 18 18 clk ce0 ce1 ce2 a[17:0] oe clk cen control clk logic data d q clk input register 16/18 16/18 16/18 oe 256k x 16/18 sram array r/ w dq [a:b] bwa bwb clk q d ft adv / ld lbo burst logic addr. registers write delay 16/18 18 zz clk logic block diagram pin arrangement for tqfp (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 lbo a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc nc a10 a11 a12 a13 a14 a15 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a ce0 ce1 nc nc bwb bwa ce2 v dd v ss clk r/w cen oe adv/ld nc nc a a tqfp 14x20mm a16 nc nc nc v ddq v ssq nc nc dqb dqb v ssq v ddq dqb dqb ft v dd nc v ss dqb dqb v ddq v ssq dqb dqb nc nc v ssq v ddq nc nc nc a17 nc nc v ddq v ssq nc dqpa, nc dqa dqa v ssq v ddq dqa dqa v ss zz dqa dqa v ddq v ssq dqa dqa nc nc v ssq v ddq nc nc nc nc v dd dqpb, selection guide -166 -133 -100 units minimum cycle time 67.510 ns maximum pipelined clock frequency 166 133 100 mhz maximum pipelined clock access time 3.5 4 5 ns maximum operating current 475 425 325 ma maximum standby current 130 100 90 ma maximum cmos standby current (dc) 30 30 30 ma note: pins 24, 74 are nc for 16 this datasheet has been downloaded from http://www.digchip.com at this page
? AS7C33256NTD16A as7c33256ntd18a 12/2/02 , v.1.7 alliance semiconductor p. 2 of 10 functional description the AS7C33256NTD16A/18a family is a high perf ormance cmos 4-mbit synchronous static ra ndom access memory (sram) organized as 262,144 words 16 or 18 bits and incorporates a late late write. this variation of the 4mb sychronous sram uses the no turnaro und delay (ntd) architecture, fea turing an enhanced write operatio n that improves bandwidth over pipelined burst de vices. in a normal pipelined burst device , the write data, command, and address are a ll applied to the device on the same clock edge. if a read command follows thi s write command, the system must wait for two 'dead' cycles for valid data to become available. these dead cycles can significantly reduce overall bandwidth for applicatio ns requiring random access or r ead-modify- write operations. ntd devices use the memory bus more efficiently by introducing a write latency that matches the two-cycle pipelined or one-cycl e flow- through read latency. write data is applied two cycles after the write command and address, allowi ng the read pipeline to clear . with ntd, write and read operations can be used in any order without producing dead bus cycles. assert r/ w low to perform write cycles. byte write enable controls write access to specific bytes, or it can be tied low for full 16/18 b it writes. write enable signals, along with the write address, are regi stered on a rising edge of the clock. write data is applied to the device two clock cycles later. unlike some asynchronous srams, output enable oe does not need to be toggled for writ e operations. it can be tied low for normal operations. outputs go to a high impedance state when the device is de selected by any of the three chip enable inputs. i n pipelined mode, a two-cycle deselect latency allows pendin g read or write operations to be completed. use the adv (burst advance) input to perform burst read, write, and deselect operations. when adv is high, external addresses, chip select, and r/w pins are ign ored, and internal address counters increme nt in the count sequence specified by the lbo control. any device operations, including burst, can be stalled using the clock enable input cen =1. the as7c33256ntd18a and AS7C33256NTD16A operate with a 3. 3v 5% power supply for the device core (v dd ). dq circuits use a separate power supply (v ddq ) that operates across 3.3v or 2.5v ranges. these devices are available in a 100-pin 1420 mm tqfp package. capacitance parameter symbol signals test conditions max unit input capacitance c in address and control pins v in = 0v 5 pf i/o capacitance c i/o i/o pins v in = v out = 0v 7 pf burst order interleaved burst order lbo = 1 linear burst order lbo = 0 starting address 00 01 10 11 starting address 00 01 10 11 first increment 01 00 11 10 first increment 01 00 11 10 second increment 10 11 00 01 second increment 10 11 00 01 third increment 11 10 01 10 third increment 11 10 01 10
? AS7C33256NTD16A as7c33256ntd18a 12/2/02 , v.1.7 alliance semiconductor p. 3 of 10 stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only an d functional operation of the device at these or any other conditions outside those indicated in the operational sections of this sp ecification is not im plied. exposure to absolute maximum rating conditions may affect reliability. signal descriptions signal i/o properties description clk i clock clock. all inputs except oe , ft , lbo , and zz are synchronous to this clock. cen i sync clock enable. when de-asserted high, the clock input signal is masked. a, a0, a1 i sync address. sampled when all chip enables are active and adv/ld is asserted. dq[a,b] i/o sync data. driven as output when the chip is enabled and oe is active. ce0 , ce1, ce2 isync synchronous chip enables. sampled at the rising edge of clk, when adv/ld is asserted. are ignored when adv/ld is high. adv/ld isync advance or load. when sampled high, the internal burst address counter will increment in the order defined by the lbo input value. (refer to table on page 2) when low, a new address is loaded. r/w isync a high during load initiates a read operation. a low during load initiates a write operation. is ignored when adv/ld is high. bw[a,b] isync byte write enables. used to control write on individual bytes. sa mpled along with write command and burst write. oe i async asynchronous output enable. i/o pins are not driven when oe is inactive. lbo istatic count mode. when driven high, count sequence follows intel xor convention. when driven low, count sequence follows linear convention. this input should be static when the device is in operation. ft istatic flow-through mode. when low, enables single register flow-through mode. connect to v dd if unused or for pipelined operation. zz i async snooze. places device in low power mode . data is retained. connect to gnd if unused. nc - - no connects. note that pin 83 and 84 will be used for future address expansion to 8mb and 16mb density. absolute maximum ratings parameter symbol min max unit power supply voltage relative to gnd v dd , v ddq ?0.5 +4.6 v input voltage relative to gnd (input pins) v in ?0.5 v dd + 0.5 v input voltage relative to gnd (i/o pins) v in ?0.5 v ddq + 0.5 v power dissipation p d ?1.8w dc output current i out ?50ma storage temperature (plastic) t stg ?65 +150 o c temperature under bias (junction) t bias ?65 +135 o c
? AS7C33256NTD16A as7c33256ntd18a 12/2/02 , v.1.7 alliance semiconductor p. 4 of 10 key : x = don?t care. l = low. h = high. 1. should be low for burst write, unless a specific byte needs to be inhibited 2. refer to state diagram below. state diagram for ntd sram synchronous truth table ce0 ce1 ce2 adv/ ld r/ w bw[a,b] oe cen address source clk operation h x x l x x x l na l to h deselect, high-z x l x l x x x l na l to h deselect, high-z x x h l x x x l na l to h deselect, high-z l h l l h x x l external l to h begin read l h l l l l x l external l to h begin write xxxhxx 1 x l burst counter l to h burst 2 x x x x x x x h stall l to h inhibit the clk tqfp thermal resistance description conditions symbol ty p i c a l units thermal resistance (junction to ambient) 1 1 this parameter is sampled. test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 1-layer ja 40 c/w 4-layer ja 22 c/w thermal resistance (junction to top of case) 1 jc 8c/w dsel dsel r ead read burst burst write read write burst read read write d s e l r e a d burst write dsel d s e l w r i t e w r it e burst dsel burst burst write read
? AS7C33256NTD16A as7c33256ntd18a 12/2/02 , v.1.7 alliance semiconductor p. 5 of 10 recommended operating conditions parameter symbol min nominal max unit supply voltage v dd 3.135 3.3 3.465 v gnd 0.0 0.0 0.0 v 3.3v i/o supply voltage v ddq 3.135 3.3 3.465 v gnd q 0.0 0.0 0.0 2.5v i/o supply voltage v ddq 2.35 2.5 2.65 v gnd q 0.0 0.0 0.0 input voltages 1 1 input voltage ranges apply to 3.3v i/o operation. for 2.5v operation, contact factory for input specifications. address and control pins v ih 2.0 ? v dd + 0.3 v v il ?0.5 2 2 v il min = ?2.0v for pulse width less than 0.2 x t rc . ?0.8v i/o pins v ih 2.0 ? v ddq + 0.3 v v il -0.5 2 ?0.8 ambient operating temperature t a 0?70c dc electrical characteristi cs for 3.3v i/o operation parameter symbol test conditions 166 133 100 unit min max min max min max input leakage current | i li | 1 1 lbo pin has an internal pull-up, and input leakage = 10 a. v dd = max, v in = gnd to v dd ?2?2?2a output leakage current | i lo | oe v ih, v dd = max, v out = gnd to v dd ?2?2?2a operating power supply current i cc 2 2 i cc given with no output loading. i cc increases with faster cycle times and greater output loading ce = v il , ce = v ih , ce = v il , f = f max, i out = 0 ma ? 450 ? 425 ? 325 ma standby power supply current i sb f = f max ? 110 ? 100 ? 90 ma i sb1 f = 0
in 0.2v or v dd - 0.2v ?30?30?30ma i sb2 deselected, f=f max , zz v dd - 0.2v all v in v il or v ih ?30?30?30ma output voltage v ol i ol = 8 ma, v ddq = 3.6v ?0.4?0.4?0.4v v oh i oh = ?4 ma, v ddq = 3.0v 2.4 ? 2.4 ? 2.4 ? v dc electrical characteristi cs for 2.5v i/o operation parameter symbol test conditions 166 133 100 unit min max min max min max output leakage current | i lo | oe v ih, v dd = max, v out = gnd to v dd -1 1 -1 1 -1 1 a output voltage v ol i ol = 2 ma, v ddq = 2.65v ? 0.7 ? 0.7 ? 0.7 v v oh i oh = ?2 ma, v ddq = 2.35v 1.7 ? 1.7 ? 1.7 ?
? AS7C33256NTD16A as7c33256ntd18a 12/2/02 , v.1.7 alliance semiconductor p. 6 of 10 timing characteristics over operating range parameter symbol 166 133 100 unit notes 1 1 see ?notes? on page 9 min max min max min max clock frequency f max - 166 - 133 - 100 mhz cycle time (pipelined mode) t cyc 6 - 7.5 - 10 - ns cycle time (flow-through mode) t cycf 10 - 12 - 12 - ns clock access time (pipelined mode) t cd -3.5-4.0-5.0ns clock access time (flow-through mode) t cdf -9-10-12ns output enable low to data valid t oe -3.5-4.0-5.0ns clock high to output low z t lzc 0 - 0 - 0 - ns 2,3,4 data output invalid from clock high t oh 1.5 - 1.5 - 1.5 - ns 4 output enable low to output low z t lzoe 0 - 0 - 0 - ns 2,3,4 output enable high to output high z t hzoe - 3.5 - 4.0 - 4.5 ns 2,3,4 clock high to output high z t hzc - 3.5 - 4.0 - 4.5 ns 2,3,4 clock high to output high z t hzcn -1.5-2.0-2.5ns5 clock high pulse width t ch 2.4 - 2.5 - 3.0 - ns 6,7 clock low pulse width t cl 2.2 - 2.5 - 3.0 - ns 6 address setup to clock high t as 1.5 - 1.5 - 1.5 - ns 7 data setup to clock high t ds 1.5 - 1.5 - 1.5 - ns 7 write setup to clock high t ws 1.5 - 1.5 - 1.5 - ns 7 chip select setup to clock high t css 1.5 - 1.5 - 1.5 - ns 7 clock enable setup to clock high t cens 1.5 - 1.5 - 1.5 - ns 7 adv setup to clock high t advs 1.5 - 1.5 - 1.5 - ns 7 address hold from clock high t ah 0.5 - 0.5 - 0.5 - ns 7 data hold from clock high t dh 0.5 - 0.5 - 0.5 - ns 7 write hold from clock high t wh 0.5 - 0.5 - 0.5 - ns 7 chip select hold from clock high t csh 0.5 - 0.5 - 0.5 - ns 7 clock enable hold from clock high t cenh 0.5 - 0.5 - 0.5 - ns 7 adv hold from clock high t advh 0.5 - 0.5 - 0.5 - ns 7
? AS7C33256NTD16A as7c33256ntd18a 12/2/02 , v.1.7 alliance semiconductor p. 7 of 10 timing waveform of read/write cycle note: y = xor when lbo = high/no connect. y = add when lbo = low. bw[a:b] is don?t care. undefined output/don?t care key to waveform

! " #$ # $ #"$ #$ # y %$ #$ #!$ #! y %$ burst write d(a2 y 01) read q(a3) read q(a4) burst read q(a4 y 01) write d(a5) read q(a6) write d(a7) dsel write d(a1) write d(a2) & & & & t t as t ah #$ # $ #"$ #$ # y %$ #$ #!$ y '('( )*+,-./, #0$
? AS7C33256NTD16A as7c33256ntd18a 12/2/02 , v.1.7 alliance semiconductor p. 8 of 10 nop, stall and deselect cycles note: oe is low.

#$ #$ y # y %$ burst q(a1 y0 1) stall dsel burst dsel write d(a2) burst nop d(a2 y 01) write nop d(a3) #$ #$ y # y %$ read q(a1) burst q(a1 y 10) burst d(a2 y 10) '('( )*,./, # y %$
? AS7C33256NTD16A as7c33256ntd18a 12/2/02 , v.1.7 alliance semiconductor p. 9 of 10 ac test conditions z 0 =50 ? d out 50 ? v l =1.5v figure b: output load (a) 30 pf* figure a: input waveform 10% 90% gnd 90% 10% +3.0v output load: for t lzc , t lzoe , t hzoe , t hzc , see figure c. for all others, see figure b. input pulse level: gnd to 3v. see figure a. input rise and fall time (measured at 0.3v and 2.7v): 2 ns. see figure a. input and output timing reference levels: 1.5v. 353 ? / 1538? 5 pf* 319 ? / 1667? d out gnd figure c: output load (b) *including scope and jig capacitance thevenin equivalent: +3.3v for 3.3v i/o, +2.5v for 2.5v i/o notes: package dimensions: 100-pin quad flat pack (tqfp) tqfp min max a1 0.05 0.15 a2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 d 13.90 14.10 e 19.90 20.10 e 0.65 nominal hd 15.90 16.10 he 21.90 22.10 l 0.45 0.75 l1 1.00 nominal a 0 7 dimensions in millimeters he e hd d b e a1 a2 l1 l c 1 for test conditions, see ac test conditions , figures a, b, and c. 2 this parameter measured with output load condition in figure c 3 this parameter is sampled and not 100% tested. 4t hzoe is less than t lzoe , and t hzc is less than t lzc at any given tempera- ture and voltage. 5 t hzcn is a no-load parameter to indicate exactly when sram outputs have stopped driving. 6t ch measured as high above vih, and t cl measured as low below vil 7 this is a synchronous device. all addr esses must meet the specified setup and hold times for all rising edges of clk. all other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clk when chip is enabled.
? copyright alliance semiconductor corporati on. all rights reserved. our three-point l ogo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all other brand and pr oduct names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance a ssumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance?s best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at a ny time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is i ntended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or l iability arising out of the application or use of any product described he rein, and disclaims any express or implied warranties related to the sale and/or use of alliance produc ts including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance?s terms and conditions of sale (which are available from alliance). all sales of allian ce products are made exclusivel y according to alliance?s terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, c opyrights, mask works rights, trademarks , or any other intellectual property rights of allian ce or third parties. alliance does not authorize its products for use as critical components in life-supporting sy stems where a malfunction or failu re may reasonably be expecte d to result in significant injury to the user, a nd the inclusion of alliance products in such life- supporting systems implies that the manufacturer assumes all risk of such use and agrees to i ndemnify alliance against all clai ms arising from such use. ? AS7C33256NTD16A as7c33256ntd18a 12/2/02 , v.1.7 alliance semiconductor p. 10 of 10 1.alliance semicond uctor sram prefix 2.operating voltage: 33 = 3.3v 3.organization: 256 = 256 k 4. ntd = no turnaround delay 5.organization: 16 = x16, 18 = x18 6.production version: a = first production version 7.clock speed (mhz) 8.package type: tq = tqfp 9.operating temperature: c = commercial ( 0 c to 70 c). i = industrial ( -40 c to 85 c) ordering information package width 166 mhz 133 mhz 100 mhz tqfp 16 AS7C33256NTD16A-166tqc as7c33256ntd 16a-133tqc AS7C33256NTD16A-100tqc tqfp 16 AS7C33256NTD16A-166tqi as7c33256ntd 16a-133tqi AS7C33256NTD16A-100tqi tqfp 18 as7c33256ntd18a-166tqc as7c33256ntd 18a-133tqc as7c33256ntd18a-100tqc tqfp 18 as7c33256ntd18a-166tqi as7c33256ntd 18a-133tqi as7c33256ntd18a-100tqi part numbering guide as7c 33 256 ntd 16/18 a ?xxx tq c/i 1 23 45678 9

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